Low temperature electrical performance of ultrathin oxide MOS capacitors with p+ poly-Si1-xGex and poly-Si gate materials

被引：0

作者：

Jacob, AP ^{[1
]}

Myrberg, T ^{[1
]}

Yousif, MYA ^{[1
]}

Nur, O ^{[1
]}

Willander, M ^{[1
]}

Lundgren, P ^{[1
]}

Sveinbjörnsson, EÖ ^{[1
]}

Caymax, M ^{[1
]}

机构：

[1] Chalmers Univ Technol, Dept Phys, Lab Phys Elect & Photon, Microtechnol Ctr MC2, S-41296 Gothenburg, Sweden

来源：

PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2 | 2002年 / 4746卷

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low temperature electrical characterization of ultra thin oxide MOS capacitors with p(+) poly-Si1-xGex and poly-Si gate is performed. The investigated structures are suitable for future nano-scaled high speed MOSFET. The aim of this study is to compare the low temperature performance of poly-Si1-xGex and poly-Si gate MOS structures in the nanoscale channel length regime. Apart from the significant change in the flat band voltage, the result shows that the accumulation capacitance of these MOS structures decreases with temperature. Though this is not significant, there is a consistency seen with respect to the temperature for poly-Si and poly-Si1-xGex gated MOS capacitors. In addition the observed results are different from the metal gated MOS structures.

引用

页码：668 / 671

页数：4

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