Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET

In this paper, we present the fabrication and electrical characterization of a MOS gated diode based on axially doped silicon nanowire (NW) p-i-n junctions. These nanowires are grown by chemical vapour deposition (CVD) using the vapour-liquid-solid (VLS) mechanism. NWs have a length of about with of doped regions (p-type and n-type) and of intrinsic region. The gate stack is composed of 15 nm of hafnium dioxide (), 80 nm of nickel and 120 nm of aluminium. At room temperature, , and an ratio of about with a very low current has been obtained. Electrical measurements are carried out between 90 and 390 K, and we show that the I (on) current is less temperature dependent below 250 K. We also observe that the ON current is increasing between 250 and 390 K. These transfer characteristics at low and high temperature confirm the tunnelling transport mechanisms in our devices.