A Domain Specific Interconnect for Reconfigurable Computing

被引：0
|
作者：
Rajopadhye, Sanjay [1 ]
Gautam [1 ]
Renganarayana, Lakshminarayanan
机构：
[1] Colorado State Univ, Ft Collins, CO 80523 USA
来源：
LCTES'08: PROCEEDINGS OF THE 2008 ACM SIGPLAN-SIGBED CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS | 2008年
关键词：
FPGA; coarse grain reconfiguration; silicon compilation;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Affine Control Loops (ACLs) occur frequently in data- and compute-intensive applications. Implementing ACLs directly on dedicated hardware has the potential for spectacular performance improvement in area, time and energy. An important challenge for such direct hardware compilation of ACLs is the interconnection between the different processing elements, which may be non-local as well as dynamic. We propose a generic, reconfigurable interconnection fabric which can realize the data-path of any ACL and be dynamically reconfigured in constant time. We have applied for a patent for this technology.
引用
收藏
页码：79 / 88
页数：10
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