Functional fault simulation of VHDL gate level models

A method of fault injection and fault simulation is being proposed here. A gate level circuit if modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be simulated using a standard VHDL simulator. A program for obtaining this model and creating a simulatable VHDL model has been developed. A comparison with other VHDL based fault simulations will be given.