A methodology for converting polygon-based standards cells from bulk CMOS to SOI CMOS

被引：0
|
作者：
Wu, KY
Chan, PCH
机构：
[1] Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology, Clear Water Bay
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1997年 / 83卷 / 04期
关键词：
D O I：
10.1080/002072197135300
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A methodology has been developed to convert polygon-based full-custom bulk CMOS cells to SOI/CMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. The methodology is demonstrated by converting the orbit scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cell this methodology may lead to a slight increase in the cell area. This methodology can also be applied to further reduce the cell area if the SOI/CMOS cells are redesigned to take advantage of the low-power and high-performance capability of SOI/CMOS. This paper presents the detailed heuristics of the methodology.
引用
收藏
页码：473 / 491
页数：19
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