Differential ECL/CML Synthesis for SiGe BiCMOS

被引:0
|
作者
Gustat, Hans [1 ]
Jagdhold, Ulrich [1 ]
Winkler, Frank [2 ]
Appel, Markus [2 ]
机构
[1] IHP Microelect, Dept Circuit Design, Frankfurt, Oder, Germany
[2] Humboldt Univ zu Berlin, Dept Comp Sci, Berlin, Germany
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel SiGe ECL/CML design flow is presented for the first time. It provides CMOS-style synthesis with differential SiGe BiCMOS ECL standard cells. A first version works in a 95GHz one-mask HBT technology up to about 10GHz clock rate. A synthesized CML/ECL FIFO buffer example with 497 ECL gates works up to 3 GHz data rate.
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页码:198 / +
页数:2
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