Research on TSV Positioning in 3D IC Placement

被引:0
|
作者
Hou, Ligang [1 ]
Bai, Shu [1 ]
Wang, Jinhui [1 ]
机构
[1] Beijing Univ Technol, VLSI & Syst Lab, Beijing 100124, Peoples R China
基金
中国国家自然科学基金;
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper forwards two TSV positioning algorithm named middle-cut positioning (MCP) and optimized area positioning ( OAP). In 3D IC placement, TSV occupies cell area and its position does affect the real wire length which is ignored in previous works. Its effect should be considered by TSV based wirelength calculation and TSV positioning. Experiments are carried out on 2D-3D transformation of IBM benchmark circuits. Results shows that OAP outrun MCP, which optimized total wirelength in 15 out of 17 benchmark circuits, in which best optimized 11.81%
引用
收藏
页数:4
相关论文
共 50 条
  • [41] Characterization of low temperature SiNx films for 3D/2.5D-IC TSV
    Kobayashi, Yasushi
    Nakata, Yoshihiro
    Nakamura, Tomoji
    Takeyama, Mayumi B.
    Sato, Masaru
    Noya, Atsushi
    IEEJ Transactions on Electronics, Information and Systems, 2015, 135 (07) : 733 - 738
  • [42] Thermal-Driven 3D Floorplanning using Localized TSV Placement
    Budhathoki, Puskar
    Henschel, Andreas
    Elfadel, Ibrahim M.
    2014 IEEE INTERNATIONAL CONFERENCE ON IC DESIGN & TECHNOLOGY (ICICDT), 2014,
  • [44] Vertical Tree 3-dimensional TSV Clock Distribution Network in 3D IC
    Kim, Dayoung
    Kim, Joohee
    Pak, Junso
    Lee, Hyungdong
    Lee, Junho
    Park, Kunwoo
    Kim, Joungho
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 1945 - 1950
  • [45] Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement
    Li, Cha-Ru
    Mak, Wai-Kei
    Wang, Ting-Chi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (03) : 523 - 532
  • [46] 3D TSV and Interposer
    Fraunhofer, Juergen Wolf
    2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2012,
  • [47] 3D IC products using TSV for mobile phone applications: An industrial perpective
    Guillou, Yann
    Dutron, Anne-Marie
    2009 EUROPEAN MICROELECTRONICS AND PACKAGING CONFERENCE (EMPC 2009), VOLS 1 AND 2, 2009, : 361 - 366
  • [48] An extensive survey on reduction of noise coupling in TSV based 3D IC integration
    Pragathi, Dadaipally
    Prasad, Dumpa
    Padma, Tatiparti
    Reddy, P. Rahul
    Kumari, Ch. Usha
    Poola, Praveen Kumar
    Panigrahy, Asisa Kumar
    MATERIALS TODAY-PROCEEDINGS, 2021, 45 : 1471 - 1480
  • [49] Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC's
    Alaises, Renold Sam Vethamuthu Edward
    Sathasivam, Sivanantham
    ELECTRONICS, 2023, 12 (04)
  • [50] RETRACTED: TSV Aware 3D IC Partitioning with Area Optimization (Retracted Article)
    Kadambarajan, Jeya Prakash
    Pothiraj, Sivakumar
    ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING, 2023, 48 (02) : 2587 - 2587