Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric

被引：3

作者：

Wang, Zheng ^{[1
]}

Walker, D. M. H. ^{[1
]}

机构：

[1] Texas A&M Univ, Dept Comp Sci & Engn, College Stn, TX 77843 USA

来源：

2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/VTS.2009.55

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs.

引用

页码：59 / 64

页数：6

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