Stability and leakage characteristics of novel conducting PMOS based 8T SRAM cell

The stability and leakage power of SRAMs have become an important issue with scaling of CMOS technology. This article reports a novel 8-transistor (8T) SRAM cell improving the read and write stability of data storage elements and reducing the leakage current in idle mode. In read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In write operation, a negative bias on the cell facilitates to change contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates 2x higher read stability while bearing 20% better write-ability at 1.2 V typical condition and a reduction by 45% in leakage power consumption compared to the standard 6T cell. Results of the bit-cell architecture were also compared to the dual-port 8T SRAM cell. The stability enhancement and leakage power reduction provided with the proposed cell are confirmed under process, voltage and temperature variations.