Process window OPC verification: Dry versus immersion lithography for the 65 nm node.

被引:0
|
作者
Borjon, Amandine [1 ,2 ,3 ,4 ,5 ]
Belledent, Jerome [1 ]
Trouiller, Yorick [3 ]
Lucas, Kevin [2 ]
Couderc, Christophe [1 ]
Sundermann, Frank [4 ]
Urbani, Jean-Christophe [4 ]
Rody, Yves [1 ]
Gardin, Christian [2 ]
Foussadier, Frank [4 ]
Schiavone, Patrick [5 ]
机构
[1] Philips Semicond, 850 Rue J Monnet, F-38926 Crolles, France
[2] Freescale Semicond, F-38926 Crolles, France
[3] CEA, LETI, F-38054 Grenoble, France
[4] STMicroelectronics, F-38926 Crolles, France
[5] CEA Grenoble, CNRS, LTM, F-38054 Grenoble 09, France
来源
关键词
OPC; resist modelling; process window; ORC; failure prediction;
D O I
10.1117/12.657056
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 rim node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study.
引用
收藏
页码:U2473 / U2483
页数:11
相关论文
共 50 条
  • [41] Development of new resist materials for 193-nm dry and immersion lithography
    Takebe, Y
    Sasaki, T
    Shirota, N
    Yokokoji, O
    [J]. MICROELECTRONIC ENGINEERING, 2006, 83 (4-9) : 1091 - 1093
  • [42] Development of new resist materials for 193-nm dry and immersion lithography
    Sasaki, Takashi
    Shirota, Naoko
    Takebe, Yoko
    Yokokoji, Osamu
    [J]. ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXIII, PTS 1 AND 2, 2006, 6153 : U247 - U254
  • [43] Resolution enhancement technology for ArF dry lithography at 65 nm node - art. no. 67240Z
    Gao, Songbo
    Li, Yanqiu
    [J]. DESIGN, MANUFACTURING, AND TESTING OF MICRO- AND NANO-OPTICAL DEVICES AND SYSTEMS, 2007, 6724 : Z7240 - Z7240
  • [44] OPC accuracy enhancement through systematic OPC calibration and verification methodology for sub-100nm node
    Yang, HJ
    Choi, JS
    Cho, BG
    Cho, BH
    Yim, D
    Kim, J
    [J]. Metrology, Inspection, and Process Control for Microlithography XIX, Pts 1-3, 2005, 5752 : 720 - 726
  • [45] Effect of process related and haze defects on 193 nm immersion lithography
    Tay, C. J.
    Quan, C.
    Ling, M. L.
    Lin, Q.
    Chua, G. S.
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2010, 28 (01): : 45 - 51
  • [46] Defect studies of resist process for 193nm immersion lithography
    Ando, Tomoyuki
    Ohmori, Katsumi
    Maemori, Satoshi
    Takayama, Toshikazu
    Ishizuka, Keita
    Yoshida, Masaaki
    Hirano, Tomoyuki
    Yokoya, Jiro
    Nakano, Katsushi
    Fujiwara, Tomoharu
    Owa, Soichi
    [J]. ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XXIII, PTS 1 AND 2, 2006, 6153 : U203 - U210
  • [47] Simulation of the 45-nm half-pitch node with 193-nm immersion lithography
    Biswas, AM
    Frauenglass, A
    Brueck, SRJ
    [J]. OPTICAL MICROLITHOGRAPHY XVII, PTS 1-3, 2004, 5377 : 1579 - 1586
  • [48] Feasibility study of double exposure lithography for 65nm & 45nm node
    Hsu, S
    Van Den Broeke, D
    Chen, JF
    Park, J
    Hsu, MCW
    [J]. Photomask and Next-Generation Lithography Mask Technology XII, Pts 1 and 2, 2005, 5853 : 252 - 264
  • [49] Optimizing manufacturability for the 65nm process node
    Pramanik, D
    Cote, M
    [J]. DESIGN AND PROCESS INTEGRATION FOR MICROELECTRONIC MANUFACTURING, 2003, : 326 - 333
  • [50] Process Variability at the 65nm node and Beyond
    Nassif, Sani R.
    [J]. PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, : 1 - 7