Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering

被引:33
|
作者
Rajan, Radha S. [1 ]
Pavan, Shanthi [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Madras 600036, Tamil Nadu, India
关键词
Compensation; continuous-time; filter; FIR DAC; oversampling; sigma-delta; ADC;
D O I
10.1109/JSSC.2014.2345023
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Continuous-time Delta Sigma modulators (CTDSM) used in wireless systems need to process signals in the presence of interferers. Peaking in the Signal Transfer Function of a conventional design necessitates a higher in-band dynamic range to accommodate interferers. A filter up front solves this problem at the expense of increased power dissipation and degraded linearity of the signal chain. Embedding the filter in the modulator achieves the same objective in a power efficient manner, while improving out-of-band linearity and reducing active area. However, having the filter inside a Delta Sigma loop can be problematic with respect to stability. We show that such a system can be stabilized in a robust manner without extra hardware. Measurements of a CTDSM (signal BW = 2 MHz), with a built-in VGA (0 to 18 dB) and a second order Butterworth filter (4 MHz cutoff), show that the in-band/out-of-band IIP3 improves by about 3/10 dB when compared to the filter-CTDSM cascade, and achieves a similar dynamic range and consumes 25% lower power.
引用
收藏
页码:2187 / 2198
页数:12
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