Behavioral simulation of fractional-N frequency synthesizers and other PLL circuits

被引：11
|
作者：
Perrott, MH [1 ]
机构：
[1] MIT, EECS, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2002年 / 19卷 / 04期
关键词：
D O I：
10.1109/MDT.2002.1018136
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulation frameworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits.
引用
收藏
页码：74 / 83
页数：10
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