Synchronous to asynchronous conversion of digital circuits

被引：0

作者：

Cassia, Ricardo ^{[1
]}

Franca, Felipe ^{[1
]}

Alves, Vladimir ^{[2
]}

机构：

[1] Univ Fed Rio de Janeiro, COPPE, PEE, PESC, BR-21945 Rio De Janeiro, Brazil

[2] Simple Tech, Santa Ana, CA USA

来源：

PRIME 2006: 2ND CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONIC AND ELECTRONICS, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work an automated conversion method of synchronous circuits into asynchronous ones is presented. The technique utilizes the synchronous circuit fully synthesized netlist, and employs ASERT - Asynchronous Scheduling by Edge Reversal Timing - for signaling and synchronization between asynchronous functional units, which are ectracted from the functional blocks hierarchical organization conceived by the original synchronous circuit designer. The method utilizes CAD tools and standard cells libraries for traditional synchronous circuits in addition to a specific developed software.

引用

页码：365 / +

页数：2

共 50 条

[41] Automatic synthesis of asynchronous circuits from synchronous RTL descriptions
Oberg, Johnny
Plosila, Juha
Ellervee, Peeter
[J]. NORCHIP 2005, PROCEEDINGS, 2005, : 200 - 205
[42] Design Of A Globally Asynchronous Locally Synchronous Digital System
Nagy, Lukas
Koscelansky, Jan
Stopjakova, Viera
[J]. 12TH IEEE INTERNATIONAL CONFERENCE ON EMERGING ELEARNING TECHNOLOGIES AND APPLICATIONS (ICETA 2014), 2014, : 529 - 533
[43] An approach to synthesis of mixed synchronous/asynchronous digital devices
Sudnitson, A
[J]. 2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, 2002, : 695 - 698
[44] A processing element for a digital asynchronous/synchronous vision chip
Lopich, Alexey
Dudek, Piotr
[J]. PROCEEDINGS OF THE FOURTH IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS, 2006, : 296 - +
[45] Asynchronous techniques for digital MESFET gallium arsenide circuits
Eshraghian, K
Lachowicz, S
[J]. DESIGN, CHARACTERIZATION, AND PACKAGING FOR MEMS AND MICROELECTRONICS, 1999, 3893 : 274 - 283
[46] Performance-based clustering for asynchronous digital circuits
Sadeghi, Rezgar
Jahanirad, Hadi
[J]. 2017 25TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE), 2017, : 238 - 243
[47] Concurrent Rewriting Semantics and Analysis of Asynchronous Digital Circuits
Katelman, Michael
Keller, Sean
Meseguer, Jose
[J]. REWRITING LOGIC AND ITS APPLICATIONS, 2010, 6381 : 140 - +
[48] State of the art in the methodologies of design of asynchronous digital circuits
Nieto-Londono, Ruben D.
Bernal-Norena, Alvaro
[J]. INGENIERIA Y COMPETITIVIDAD, 2005, 7 (02): : 71 - 83
[49] Asynchronous circuits and systems in superconducting RSFQ digital technology
Deng, ZJ
Yoshikawa, N
Tierno, JA
Whiteley, SR
Van Duzer, T
[J]. ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS - FOURTH INTERNATIONAL SYMPOSIUM, 1998, : 274 - 285
[50] LAMP - AUTOMATIC TEST GENERATION FOR ASYNCHRONOUS DIGITAL CIRCUITS
CHAPPELL, SG
[J]. BELL SYSTEM TECHNICAL JOURNAL, 1974, 53 (08): : 1477 - 1503

← 1 2 3 4 5 →