Interconnect estimation for FPGAs

Interconnect planning is becoming an important design issue for large field programmable gate array (FPGA)-based designs. One of the most important issues for planning interconnection is the ability to reliably predict the routing requirements of a given design. In this paper, a new methodology, called fast generic routability estimation for placed FPGA circuits (fGREP), for fast and reliable estimation of routing requirements for placed circuits con island-style FPGAs, is introduced. This method is based on newly derived detailed router characterizations that are introduced in this paper. It is observed that the router has a limited number of available routing elements to use and the number is proportional to the distance from a net's terminal. This is defined is the routing flexibility and an estimate for interconnect requirements is derived from it. This method is able to predict the distribution of interconnect requirements, with very fine granularity, across the entire device. The interconnect-distribution information is used to estimate congestion and total wirelength. Multiterminal nets are efficiently handled, without the need for net decomposition. This method is generic enough to enable its usage with, any standard FPGA place-and-route design How and for any island-style FPGA architecture. The method is also applicable to application-specific integratcd circuit (ASIC) design flows. Experimental results on a large set of standard benchmark examples show that the estimates obtained here closely match with the detailed routing results of the state-of-the-art router PathFinder [1], as implemented in the well-known FPGA physical design suite VPR [2].