On the VLSI Energy Complexity of LDPC Decoder Circuits

Sequences of randomly generated bipartite configurations are analyzed; under mild conditions almost surely such configurations have minimum bisection width proportional to the number of vertices. This implies an almost sure Omega (n(2)/d(max)(2)) scaling rule for the energy of directly-implemented low-density parity-check (LDPC) decoder circuits for codes of block length n and maximum node degree dmax. It also implies an Omega (n(3/2)/d(max)) lower bound for serialized LDPC decoders. It is also shown that all (as opposed to almost all) capacity-approaching, directly-implemented non-split-node LDPC decoding circuits, have energy, per iteration, that scales as Omega (X-2 ln(3)X), where X = (1 - R/C)(-1) is the reciprocal gap to capacity, R is code rate, and C is channel capacity.