Testing and design of CMOS D-latches

被引：0
|
作者：
Aissi, C
Olaniyan, J
机构：
[1] Howard Univ, Washington, DC, United States
来源：
JOURNAL OF TESTING AND EVALUATION | 1997年 / 25卷 / 01期
关键词：
CMOS D-latch; digital circuits; fully testable D-latch (FTD); transistor;
D O I：
暂无
中图分类号：
TB3 [工程材料学];
学科分类号：
0805 ; 080502 ;
摘要：
The CMOS D-latch is an important block in the design of sequential circuits. Thus, a new fully testable CMOS D-latch (FTD) is proposed. A comprehensive test set that includes possible physical failures is developed. This test set is then applied to the FTD. The cost of implementation, analysis, and simulation of the FTD are all presented. Application of the FTD-latch to build a polarity-hold shift register is shown.
引用
收藏
页码：52 / 60
页数：9
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