A CMOS high-speed multistage preamplifier for comparator design

被引：0

作者：

Fan, XP ^{[1
]}

Chan, PK ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new multistage preamplifier with offset reduction for use in high-speed comparator is presented. The proposed circuit is based on the cascade of the modified input offset storage amplifiers and the output offset storage amplifier in pipeline arrangement. Not only does the topology maintain a good input common-mode range, it exhibits faster speed due to reduced capacitive loads. Using AMS 0.35mum CMOS process model, the simulation result has shown that the new preamplifier has achieved a settling time of 3.5 ns at 1% accuracy for a transient step of 400 mV, which is faster than the conventional works at identical process and identical power consumption.

引用

页码：545 / 548

页数：4

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