The Design of a Low-Power High-Speed Current Comparator in 0.35-μm CMOS Technology

被引：6

作者：

Ziabakhsh, Soheil ^{[1
]}

Alavi-Rad, Hosein ^{[1
]}

Alavi-Rad, Mohammad ^{[2
]}

Mortazavi, Mohammad ^{[3
]}

机构：

[1] Univ Guilan, Fac Engn, Rasht, Iran

[2] Sharif Univ Technol, Dept Elect Engn, Tehran, Iran

[3] Sharif Univ Technol, Dept Sci & Engn, Kish, Iran

来源：

ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 | 2009年

关键词：

Current Comparator; Propagation Delay; Instantaneous Power; Positive Feedback; Signal Processing; CIRCUITS;

D O I：

10.1109/ISQED.2009.4810278

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 mu W for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology.

引用

页码：107 / +

页数：2

共 50 条

[1] DESIGN OF A LOW-POWER HIGH-SPEED COMPARATOR IN 0.13μm CMOS
Fouzy, B. B. A.
Reaz, M. B. I.
Bhuiyan, M. A. S.
Badal, M. T. I.
Hashim, F. H.
[J]. 2016 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRICAL, ELECTRONIC AND SYSTEMS ENGINEERING (ICAEES), 2016, : 289 - 292
[2] Low-power high-speed current comparator design
Banks, D.
Toumazou, C.
[J]. ELECTRONICS LETTERS, 2008, 44 (03) : 171 - U2
[3] A robust high-speed and low-power CMOS current comparator circuit
Chen, L
Shi, BX
Lu, C
[J]. 2000 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: ELECTRONIC COMMUNICATION SYSTEMS, 2000, : 174 - 177
[4] An advanced 0.35 mu m shallow SIMOX/CMOS technology for low-power, high-speed applications
Kaneko, S
Naka, T
Adan, AO
Kagisawa, A
[J]. PROCEEDINGS OF THE SEVENTH INTERNATIONAL SYMPOSIUM ON SILICON-ON-INSULATOR TECHNOLOGY AND DEVICES, 1996, 96 (03): : 406 - 413
[5] Design and Implementation of a Low-Power, High-Speed Comparator
Deepika, V.
Singh, Sangeeta
[J]. 2ND INTERNATIONAL CONFERENCE ON NANOMATERIALS AND TECHNOLOGIES (CNT 2014), 2015, 10 : 314 - 322
[6] A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology
Vaucher, CS
Ferencic, I
Locher, M
Sedvallson, S
Voegeli, U
Wang, ZH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (07) : 1039 - 1045
[7] Design of High-Speed and Low-Power Comparator in Flash ADC
Zhang, Shaozhen
Li, Zheying
Ling, Bo
[J]. 2012 INTERNATIONAL WORKSHOP ON INFORMATION AND ELECTRONICS ENGINEERING, 2012, 29 : 687 - 692
[8] Device integration of a 0.35 mu m CMOS on shallow SIMOX technology for high-speed and low-power applications.
Adan, AO
Naka, T
Kaneko, S
Urabe, D
Higashi, K
Kagisawa, A
[J]. 1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 116 - 117
[9] Design and simulated annealing optimization of a static comparator for low-power high-speed CMOS VLSI
Kheradmand-Boroujeni, B
Shojaee, K
Afzali-Kusha, A
[J]. 17th ICM 2005: 2005 International Conference on Microelectronics, Proceedings, 2005, : 355 - 359
[10] Low-power, high-speed CMOS VLSI design
Kuroda, T
[J]. ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 310 - 315

← 1 2 3 4 5 →