Sub-20 nm Gate Length FinFET Design: Can High-κ Spacers Make a Difference?

被引：0

作者：

Sachid, Angada B. ^{[1
]}

Francis, Roswald ^{[1
]}

Baghini, Maryam Shojaei ^{[1
]}

Sharma, Dinesh K. ^{[1
]}

Bach, Karl-Heinz ^{[2
]}

Mahnkopf, Reinhard ^{[2
]}

Rao, V. Ramgopal ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Ctr Excellence Nanotechnol, Bombay, Maharashtra, India

[2] Infineon Technol AG, Munich, Germany

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (T-FIN) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs. While comparing different FinFETs, we propose ON-current per fin as the parameter to be optimized instead of ON-current normalized to electrical width.

引用

页码：697 / +

页数：3

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