Simulations of Sub-100 nm Strained Si MOSFETs with High-κ Gate Stacks

被引：0
|
作者：
L. Yang
J. R. Watling
F. Adamu-Lema
A. Asenov
J. R. Barker
机构：
[1] University of Glasgow,Device Modeling Group, Department of Electronics and Electrical Engineering
来源：
Journal of Computational Electronics | 2004年 / 3卷
关键词：
device simulation; strained Si; MOSFET; high-κ;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
By including soft-optical phonon scattering within an ensemble Monte Carlo simulator, this paper studies the impact of high-κ gate stacks on the performance of n-type Si and strained Si MOSFETs. The simulated devices replicate the performance of sub-100 nm Si and strained Si MOSFETs fabricated by IBM. The results indicate a significant reduction in the device performance due to the presence of a high-κ gate dielectric in both Si and strained Si transistors.
引用
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页码：171 / 175
页数：4
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