An approach for detecting multiple faulty FPGA logic blocks

被引：13

作者：

Huang, WK ^{[1
]}

Meyer, FJ

Lombardi, F

机构：

[1] Fudan Univ, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China

[2] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA

来源：

IEEE TRANSACTIONS ON COMPUTERS | 2000年 / 49卷 / 01期

关键词：

FPGA; PLD; multiple faults; C-testability; fault tolerance;

D O I：

10.1109/12.822563

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An approach is proposed to test FPGA logic blocks, including part of the configuration memories used to control them. The proposed AND tree and OR tree-based testing structure is simple and the conditions for constant testability can easily be satisfied. Test generation for only a single logic block is sufficient. We do not assume any particular fault model. Any number of faulty blocks in the chip can be detected. Members of the Xilinx XC3000, XC4000, and XC5200 families were studied. The proposed AND/OR approach was found to reduce the number of FPGA reprogrammings needed for testing;by up to a factor of seven versus direct methods of multiple faulty block detection.

引用

页码：48 / 54

页数：7

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