Design and Implementation of a Field Programmable CRC Circuit Architecture

被引：18
|
作者：
Toal, Ciaran [1 ]
McLaughlin, Kieran [1 ]
Sezer, Sakir [1 ]
Yang, Xin [1 ]
机构：
[1] Queens Univ Belfast, ECIT, Belfast BT3 9DT, Antrim, North Ireland
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2009年 / 17卷 / 08期
基金：
英国工程与自然科学研究理事会;
关键词：
Cyclic redundancy check (CRC); error detection; field programmable; network processing; reconfigurable;
D O I：
10.1109/TVLSI.2008.2008741
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s.
引用
收藏
页码：1142 / 1147
页数：6
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