A 10-bit 1GSample/s DAC in 90nm CMOS for embedded applications

被引：7

作者：

Cao, Jing ^{[1
,2
]}

Lin, Haiqing ^{[1
]}

Xiang, Yihai ^{[1
]}

Kao, Chungpao ^{[1
]}

Dyer, Ken

机构：

[1] KT Micro Inc, Rancho Santa Margarita, CA USA

[2] Keyeye Commun, Sacramento, CA USA

来源：

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

10.1109/CICC.2006.320871

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 90 nm CMOS 10-bit 1 GS/s current-steering D/A converter is presented. It is designed and optimized for next generation high-speed digital communication SoCs. With only five power/ground pins and a 10-bit architecture, 72 dB SFDR and 9.2 ENOB are measured with a full-scale 41.3 MHz input at 800 MS/s. At 1.05 GS/s, 68 dB SFDR is achieved for a full-scale 54.3 MHz input. It dissipates a core power of 49 mW, the lowest power consumption reported at this performance level, and occupies a die area of merely 0.36 nm. The monolithic DAC is fabricated in TSMC 1P9M 90mn CMOS process.

引用

页码：165 / 168

页数：4

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