Multi-column parallel QC-LDPC decoder architecture for NAND flash memory

被引：0
|
作者：
Shen, Wei [1 ]
Chen, Cheng [2 ]
Sha, Jin [3 ]
机构：
[1] Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210046, Jiangsu, Peoples R China
[2] ZTE Corp, Microelect R&D Inst, Nanjing 210046, Jiangsu, Peoples R China
[3] Nanjing Univ, Shenzhen Res Inst, Nanjing 210046, Jiangsu, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 10期
基金：
国家重点研发计划; 中国国家自然科学基金;
关键词：
QC-LDPC; NAND flash memory; column-based shuffle decoding; multiple-columns;
D O I：
10.1587/elex.15.20180397
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Quasi-cyclic (QC) low-density parity-check (LDPC) codes are famous for their excellent error correction performance and hardware friendly structure in NAND flash memory application. Array LDPC code is a type of highly structured QC-LDPC code that provides a good balance between performance and complexity. In this paper, a method is proposed for the construction of (18900, 17010) LDPC code that is based on the Latin square and an improved array dispersion strategy to achieve multi-column alignment of the structure. Compared with traditional design, the parallel hardware architecture reduces the number of barrel shifters by 32%. The corresponding ASIC implementation results show that the throughput of the proposed QC-LDPC code was up to 3.49 Gb/s and the throughput-to-area (TAR) of the proposed codes was significantly improved.
引用
收藏
页数：10
相关论文
共 50 条
  • [31] A low complexity LDPC-BCH concatenated decoder for NAND flash memory
    Chen, Zhongjie
    Sha, Jin
    Zhang, Chuan
    Yan, Feng
    IEICE ELECTRONICS EXPRESS, 2018, 15 (11):
  • [32] Protograph QC-LDPC and Rate-Adaptive Polar Codes Design for MLC NAND Flash Memories
    Kong, Lingjun
    Liu, Yahui
    Liu, Haiyang
    Zhao, Shengmei
    IEEE ACCESS, 2019, 7 : 37131 - 37140
  • [33] A Low Complexity Parallel QC-LDPC Encoder
    Yao, Xiaoxia
    Li, Lintao
    Liu, Jihong
    Li, Qian
    2021 IEEE MTT-S INTERNATIONAL WIRELESS SYMPOSIUM (IWS 2021), 2021,
  • [34] Multi-mode message passing switch networks applied for QC-LDPC decoder
    Liu, Chih-Hao
    Lin, Chien-Ching
    Chang, Hsie-Chia
    Lee, Chen-Yi
    Hsu, Yarsun
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 752 - +
  • [35] A Shared Hard Decisions Storing in Partially Parallel FPGA-based QC-LDPC Decoder
    Xie, Tianjiao
    Yuan, Ruijia
    Zhang, Jianhua
    2015 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION PROBLEM-SOLVING (ICCP), 2015, : 594 - 596
  • [36] Implementation of QC-LDPC Decoder Based on FPGA for FSO System
    Qiong, Yan Guo
    Hua, Zhou Mao
    MECHANICAL COMPONENTS AND CONTROL ENGINEERING III, 2014, 668-669 : 1269 - +
  • [37] Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture
    Tram Thi Bao Nguyen
    Lee, Hanho
    2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2018, : 210 - 211
  • [38] High-throughput DOCSIS Upstream QC-LDPC Decoder
    Wu, Michael
    Yin, Bei
    Miller, Eric
    Dick, Chris
    Cavallaro, Joseph R.
    CONFERENCE RECORD OF THE 2014 FORTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, 2014, : 537 - 541
  • [39] Efficient Network for Non-Binary QC-LDPC Decoder
    Zhang, Chuan
    Sha, Jin
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 2617 - 2620
  • [40] Ultra Low Power QC-LDPC Decoder with High Parallelism
    Cui, Ying
    Peng, Xiao
    Chen, Zhixiang
    Zhao, Xiongxin
    Lu, Yichao
    Zhou, Dajiang
    Goto, Satoshi
    2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC), 2011, : 142 - 145
12345