A study on wiring pattern design for intelligent SiC power module with PEEC method

被引：0
|
作者：
Masuda, Eisuke [1 ]
Ibuchi, Takaaki [1 ]
Funaki, Tsuyoshi [1 ]
Otake, Hirotaka [2 ]
Miyazaki, Tatsuya [2 ]
Kanetake, Yasuo [2 ]
Nakamura, Takashi [2 ]
机构：
[1] Osaka Univ, Osaka, Japan
[2] ROHM Co Ltd, Kyoto, Japan
来源：
2017 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | 2017年
关键词：
SiC power module; parasitic inductance; partial element equivalent circuit method; current distribution; MODELS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The fast switching operation of wide-bandgap power semiconductor devices deteriorates the Electromagnetic interference (EMI) noise characteristics of a power converter. The parasitic inductance in a power module is one cause of noise generator. This paper calculates parasitic inductance in a wiring pattern of module with Partial Element Equivalent Circuit (PEEC) method, and evaluates the current distribution in a module by magnetic near-field intensity measurement to discuss the suitable wiring pattern design for intelligent silicon carbide (SiC) power module.
引用
收藏
页码：213 / 215
页数：3
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