System-Level Power-Performance Efficiency Modeling for Emergent GPU Architectures

被引:0
|
作者
Song, Shuaiwen [1 ]
Cameron, Kirk W. [1 ]
机构
[1] Virginia Tech, CS Dept, KWII, Blacksburg, VA 24060 USA
关键词
Runtime statistical model; Power; Performance; System-wide; energy consumption; Analytical Model; GPGPU; CUDA;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:473 / 473
页数:1
相关论文
共 50 条
  • [31] Abstract System-Level Models for Early Performance and Power Exploration
    Gerstlauer, Andreas
    Chakravarty, Suhas
    Kathuria, Manan
    Razaghi, Parisa
    2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2012, : 213 - 218
  • [32] Improving System-level performance and robustness in power line monitoring
    Gil, Lluis Beltran
    Electronics World, 2024, 129 (2041): : 22 - 24
  • [33] Architecture level power-performance tradeoffs for pipelined designs
    Ali, Haider
    Al-Hashirni, Bashir M.
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1791 - 1794
  • [34] System-level power/performance analysis for embedded systems design
    Nandi, A
    Marculescu, R
    38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 599 - 604
  • [35] Power estimation of system-level buses for microprocessor-based architectures: A case study
    Politecnico di Milano, Milano, Italy
    Proc IEEE Int Conf Comput Des VLSI Comput Process, (131-136):
  • [36] Incorporating PVT variations in system-level power exploration of on-chip communication architectures
    Pasricha, Sudeep
    Park, Young-Hwan
    Kurdahi, Fadi J.
    Dutt, Nikil
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 363 - 370
  • [37] System-Level Runtime Mapping Exploration of Reconfigurable Architectures
    Sigdel, Kamana
    Thompson, Mark
    Pimentel, Andy D.
    Galuzzi, Carlo
    Bertels, Koen
    2009 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-5, 2009, : 2921 - +
  • [38] Modeling Power Supply Noise Effects for System-Level Simulation of ΔΣ-ADCs
    Meier, Jonas
    Speicher, Fabian
    Beyerstedt, Christoph
    Saalfeld, Tobias
    Boronowsky, Gregor
    Wunderlich, Ralf
    Heinen, Stefan
    2019 16TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD 2019), 2019, : 265 - 268
  • [39] A formal framework for modeling and analysis of system-level dynamic power management
    Yardi, S
    Channakeshava, K
    Hsiao, MS
    Martin, TL
    Ha, DS
    2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2005, : 119 - 126
  • [40] Advanced Modeling Techniques for System-level Power Integrity and EMC Analysis
    Graziosi, Giovanni
    Doriol, Patrice Joubert
    Villavicencio, Yamarita
    Forzan, Cristiano
    Rotigni, Mario
    Pandini, Davide
    2009 EUROPEAN MICROELECTRONICS AND PACKAGING CONFERENCE (EMPC 2009), VOLS 1 AND 2, 2009, : 52 - +