System-Level Power-Performance Efficiency Modeling for Emergent GPU Architectures

被引：0
|
作者：
Song, Shuaiwen [1 ]
Cameron, Kirk W. [1 ]
机构：
[1] Virginia Tech, CS Dept, KWII, Blacksburg, VA 24060 USA
来源：
PROCEEDINGS OF THE 21ST INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES (PACT'12) | 2012年
关键词：
Runtime statistical model; Power; Performance; System-wide; energy consumption; Analytical Model; GPGPU; CUDA;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：473 / 473
页数：1
相关论文
共 50 条
  • [1] A Simplified and Accurate Model of Power-Performance Efficiency on Emergent GPU Architectures
    Song, Shuaiwen
    Su, Chunyi
    Rountree, Barry
    Cameron, Kirk W.
    IEEE 27TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS 2013), 2013, : 673 - 686
  • [2] System-level power-performance tradeoffs for reconfigurable computing
    Noguera, Juanjo
    Badia, Rosa M.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (07) : 730 - 739
  • [3] Three Steps To Model Power-Performance Efficiency for Emergent GPU-Based Parallel Systems
    Song, Shuaiwen Leon
    2012 SC COMPANION: HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SCC), 2012, : 1344 - 1344
  • [4] Three Steps To Model Power-Performance Efficiency for Emergent GPU-Based Parallel Systems
    Song, Shuaiwen Leon
    Su, Chun-yi
    Rountree, Barry
    Cameron, Kirk W.
    2012 SC COMPANION: HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SCC), 2012, : 1345 - +
  • [5] Power-performance system-level exploration of a MicroSPARC2-based embedded architecture
    Palermo, G
    Silvano, C
    Zaccaria, V
    DESIGNERS FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2003, : 182 - 187
  • [6] A System-Level Modeling Methodology for Performance-Driven Component Selection in Multicore Architectures
    Agarwal, Ankur
    Hamza-Lup, Georgiana L.
    Khoshgoftaar, Taghi M.
    IEEE SYSTEMS JOURNAL, 2012, 6 (02): : 317 - 328
  • [7] A Framework for System-Level Modeling and Simulation of Embedded Systems Architectures
    Erbas, Cagkan
    Pimentel, Andy D.
    Thompson, Mark
    Polstra, Simon
    EURASIP JOURNAL ON EMBEDDED SYSTEMS, 2007, (01)
  • [8] Power analysis of system-level on-chip communication architectures
    Lahiri, K
    Raghunathan, A
    INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 236 - 241
  • [9] System-level I/O power modeling
    Pinello, WP
    Patel, PR
    Li, YL
    MICROELECTRONIC YIELD, RELIABILITY, AND ADVANCED PACKAGING, 2000, 4229 : 217 - 220
  • [10] Power-performance Analysis of Metaheuristic Search Algorithms on the GPU
    Connors, Tiffany
    Qasem, Apan
    2015 SIXTH INTERNATIONAL GREEN COMPUTING CONFERENCE AND SUSTAINABLE COMPUTING CONFERENCE (IGSC), 2015,
12345