An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm

This paper describes a motion estimation (ME) processor core for realtime, MP@HL video encoding. It is being fabricated with 0.13um CMOS technology and contains approximately 7 M-transistors on 4.50mm x 3.35mm area. The estimated power consumption is less than 100mW at 81MHz@1.0V. It features a Gradient Descent Search (GDS) algorithm that drastically reduces the required computation power to 7GOPS, an optimized SIMD datapath architecture that decreases the clock frequency and the operating voltage, and a low power 3-port data cache SRAM with a write-disturb-free cell array arrangement. The core can be applicable to a portable HDTV codec system.