A 95 mW MPEG2 MP@HL motion estimation processor core for portable high-resolution video application

被引：10

作者：

Murachi, Y ^{[1
]}

Hamano, K

Matsuno, T

Miyakoshi, J

Miyama, M

Yoshimoto, M

机构：

[1] Kanazawa Univ, Fac Engn, Kanazawa, Ishikawa 9208667, Japan

[2] Kobe Univ, Fac Engn, Kobe, Hyogo 6578501, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2005年 / E88A卷 / 12期

关键词：

low power; motion estimation; MPEG2; HDTV; IP;

D O I：

10.1093/ietfec/e88-a.12.3492

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 1920 x 1080 @ 30 fps resolution video. The search range is +/- 128 x +/- 64 pixels. The ME core integrates 2.25 M transistors in 3.1 mm x 3.1 mm using 0.18-micron technology.

引用

页码：3492 / 3499

页数：8

共 20 条

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Miyakoshi, J
Miyama, M
Yoshimoto, M
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