High-level symbolic simulation for automatic model extraction

被引：2
|
作者：
Ouchet, Florent [1 ]
Borrione, Dominique [1 ]
Morin-Allory, Katell [1 ]
Pierre, Laurence [1 ]
机构：
[1] UJF, CNRS, Grenoble INP, TIMA Lab, Grenoble, France
来源：
PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2009年
关键词：
Hardware design language; simulation software; circuit simulation;
D O I：
10.1109/DDECS.2009.5012132
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.
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页码：218 / 221
页数：4
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