Energy model of networks-on-chip and a bus

被引：40

作者：

Wolkotte, Pascal T. ^{[1
]}

Smit, Gerard J. M. ^{[1
]}

Kavaldjiev, Nikolay ^{[1
]}

Becker, Jens E. ^{[1
]}

Becker, Juergen ^{[1
]}

机构：

[1] Univ Twente, Dept EEMCS, NL-7500 AE Enschede, Netherlands

来源：

2005 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISSOC.2005.1595650

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-on-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

引用

页码：82 / 85

页数：4

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