Energy model of networks-on-chip and a bus

被引：40

作者：

Wolkotte, Pascal T. ^{[1
]}

Smit, Gerard J. M. ^{[1
]}

Kavaldjiev, Nikolay ^{[1
]}

Becker, Jens E. ^{[1
]}

Becker, Juergen ^{[1
]}

机构：

[1] Univ Twente, Dept EEMCS, NL-7500 AE Enschede, Netherlands

来源：

2005 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISSOC.2005.1595650

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-on-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

引用

页码：82 / 85

页数：4

共 50 条

[21] Statistical Approach to Networks-on-Chip
Cohen, Itamar
Rottenstreich, Ori
Keslassy, Isaac
[J]. IEEE TRANSACTIONS ON COMPUTERS, 2010, 59 (06) : 748 - 761
[22] eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
Beldachi, Arash Farhadi
Hollis, Simon
Nunez-Yanez, Jose L.
[J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2014, 8 (03): : 148 - 162
[23] A Simplified Executable Model to Evaluate Latency and Throughput of Networks-on-Chip
Ost, Luciano
Moraes, Fernando G.
Moeller, Leandro
Indrusiak, Leandro Soares
Glesner, Manfred
Maatta, Sanna
Nurmi, Jari
[J]. SBCCI 2008: 21ST SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2008, : 170 - 175
[24] A delay model for networks-on-chip output-queuing router
Elmiligi, Haytham
El-Kharashi, M. Watheq
Gebali, Fayez
[J]. 6TH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2006, : 95 - +
[25] Mobile Networks-on-Chip Mapping Algorithms for Optimization of Latency and Energy Consumption
Kumar, Arvind
Sehgal, Vivek Kumar
Dhiman, Gaurav
Vimal, S.
Sharma, Ashutosh
Park, Sangoh
[J]. MOBILE NETWORKS & APPLICATIONS, 2022, 27 (02): : 637 - 651
[26] Simulation environment for link energy estimation in networks-on-chip with virtual channels
Joseph, Jan Moritz
Bamberg, Lennart
Hajjar, Imad
Schmidt, Robert
Pionteck, Thilo
Garcia-Ortiz, Alberto
[J]. INTEGRATION-THE VLSI JOURNAL, 2019, 68 : 147 - 156
[27] Mobile Networks-on-Chip Mapping Algorithms for Optimization of Latency and Energy Consumption
Arvind Kumar
Vivek Kumar Sehgal
Gaurav Dhiman
S. Vimal
Ashutosh Sharma
Sangoh Park
[J]. Mobile Networks and Applications, 2022, 27 : 637 - 651
[28] A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip
He, Yuan
Kondo, Masaaki
Nakada, Takashi
Sasaki, Hiroshi
Miwa, Shinobu
Nakamura, Hiroshi
[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2016, E99D (12): : 2881 - 2890
[29] Self-calibrating networks-on-chip
Worm, F
Thiran, P
de Micheli, G
Ienne, P
[J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2361 - 2364
[30] Network Adapter for Secure Networks-on-Chip
Haase, Julian
Volkens, Nico
Goehringer, Diana
[J]. 2024 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, IPDPSW 2024, 2024, : 192 - 192

← 1 2 3 4 5 →