A Markovian performance model for networks-on-chip

Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Thus, it is of crucial importance for a designer to have access to fast methods for evaluating the performance of on-chip network. To this end, we present a Markovian model for evaluating the latency and energy consumption of on-chip networks, We compute the average delay due to path contention, virtual channel and crossbar switch arbitration using a queuing-based approach, which can capture the blocking phenomena of wormhole switching quite accurately. The model is then used to estimate the power consumption of all routers m NoCs The performance results from the analytical models are validated with those obtained from a synthesizable VHDL-based cycle accurate simulator Comparison with simulation results indicate that the proposed analytical model quite accurate and can be used as an efficient design tool by SoC designers.