VLSI architectures for field programmable gate arrays: A case study

The ability to achieve highly efficient hardware implementations of algorithms will form a key aspect in the success of custom computing. Developments in VLSI architectures where regularity, simple design and locality of connections appears to be an ideal approach in the development of efficient Field Programmable Gate Array (FPGA) designs. In this paper we present a case study namely the implementation of the majority of a two dimensional (20) Discrete Cosine Transform (DCT) in a Xilinx XC6216 device. The design has a 70% hardware utilisation figure and operates at 25 Mega pixels per second or over 30 frames per second for standard NTSC. The paper clearly demonstrates the hardware efficiency of such an approach. The paper also describes work on architectural synthesis framework to automatically generate highly regular designs for a wider range of complex algorithms.