共 50 条
- [31] Performance Evaluation of a Reconfigurable Instruction Set Processor [J]. ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 184 - +
- [32] BLAS on the trident processor: Implementation and performance evaluation [J]. COMPUTERS AND THEIR APPLICATIONS, 2003, : 359 - 364
- [34] Design and Performance Evaluation of Data Flow Processor [J]. 2014 9TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA (CHINACOM), 2014, : 578 - 582
- [35] BRUNO: A High Performance Traffic Generator for Network Processor [J]. PROCEEDINGS OF THE 2008 INTERNATIONAL SYMPOSIUM ON PERFORMANCE EVALUATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS, 2008, : 526 - 533
- [37] Implementation and evaluation of a dynamically routed processor operand network [J]. NOCS 2007: FIRST INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, PROCEEDINGS, 2007, : 7 - +
- [38] The impact of parallel and multithread mechanism on network processor performance [J]. GCC 2005: FIFTH INTERNATIONAL CONFERENCE ON GRID AND COOPERATIVE COMPUTING, PROCEEDINGS, 2006, : 236 - +
- [39] Design of a High Performance Traffic Generator on Network Processor [J]. 11TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN - ARCHITECTURES, METHODS AND TOOLS : DSD 2008, PROCEEDINGS, 2008, : 438 - 441
- [40] Calipers: A Criticality-aware Framework for Modeling Processor Performance [J]. PROCEEDINGS OF THE 36TH ACM INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, ICS 2022, 2022,