Modeling the Influence of Interface Traps on the Transfer Characteristics of In As Tunnel-FETs and MOSFETs

We present a numerical study based on a full quantum transport model to investigate the effects of interface traps in nanowire InAs Tunnel-FETs and MOSFETs by varying the trap energy level, its position and the working temperature. Our 3-D self-consistent simulations show that in Tunnel-FETs even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; shallow traps have the largest impact on subthreshold slope; and the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the Tunnel-FET characteristics. The impact of traps on the IV characteristics of MOSFETs is instead less dramatic, and the traps induced degradation of the subthreshold swing can be effectively contrasted by an aggressive oxide thickness scaling. Finally, we present a comparative analysis of the impact of interface traps on the performance variability of nanowire InAs Tunnel-FETs and MOSFETs by considering random distributions of traps.