Static Noise Margin and Power Dissipation Analysis of various SRAM Topologies

In this paper we analyze and compare 8 different SRAM cell topologies that are suitable for low power embedded memory design in terms of power consumption, area, static noise margin (SNM) and read and write delays, which are the basic parameters affecting the performance of an SRAM cell. The circuit simulation and analysis were carried out using HSPICE for 45 nm technology node. The SNM of each cell is examined analytically using SLL (Seevinck, List and Lohstroh) method. Throughout the design and analysis VDD is kept at 1.2V. For the determination of Read and Write Margin of SRAM cells, the cell ratio is kept at 3 and the pull up ratio is kept at 2 throughout the design. Our results will enable memory circuit designers to choose the appropriate SRAM cell for the required SNM and power consumption.