Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

被引：18
|
作者：
Sharaf, KM
Elmasry, MI
机构：
[1] VLSI Research Group, Dept. of Elec. and Comp. Engineering, University of Waterloo
[2] AinShams University, Cairo
[3] Cairo University, Cairo
[4] University of Ottawa, Ottawa, Ont.
[5] Bell-Northern Research, Ottawa, Ont.
[6] Dept. of Elec. and Comp. Engineering, University of Waterloo, Waterloo, Ont.
[7] AT and T Bell Labs., GE
[8] Micro Components Organization, Burroughs Corporation (Unisys), San Diego, CA
[9] Kuwait University, Kuwait, Swiss Fed. Institute of Technology, Lausanne
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1996年 / 31卷 / 02期
基金：
加拿大自然科学与工程研究理事会;
关键词：
D O I：
10.1109/4.487997
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented, The analytical delay model accounts for all the device parasitics and the device sizes of the two levels, Moreover, high-current effects are also considered in the developed model, Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay), A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.
引用
收藏
页码：202 / 211
页数：10
相关论文
共 50 条
  • [31] RISE TIME OPTIMIZATION OF HIGH-SPEED DIGITAL FANOUT CIRCUITS
    BARNA, A
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1969, SC 4 (03) : 159 - &
  • [32] INP/INGAAS DHBTS FOR HIGH-FREQUENCY AND HIGH-SPEED ECL CIRCUITS USING A SUBMICRON-MODEL
    OUACHA, A
    WILLANDER, M
    SOLID-STATE ELECTRONICS, 1991, 34 (06) : 565 - 571
  • [33] DESIGN TECHNIQUES FOR LOW-VOLTAGE HIGH-SPEED DIGITAL BIPOLAR CIRCUITS
    RAZAVI, B
    OTA, Y
    SWARTZ, RG
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (03) : 332 - 339
  • [34] Si-Ge heterojunction bipolar technology for high-speed integrated circuits
    Ahlgren, DC
    Gilbert, M
    Jeng, SJ
    Malinowski, J
    NguyenNgoc, D
    Schonenberg, K
    Stein, K
    Sunderland, D
    Soyuer, M
    Meyerson, B
    Harame, D
    CANADIAN JOURNAL OF PHYSICS, 1996, 74 : S159 - S166
  • [35] NON-QUASI-STATIC EFFECTS IN ADVANCED HIGH-SPEED BIPOLAR CIRCUITS
    WU, BS
    CHUANG, CT
    CHIN, K
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (05) : 613 - 617
  • [36] HIGH-SPEED COMMUNICATIONS CIRCUITS
    WILLIAMS, J
    EDN, 1991, 36 (23) : 233 - 241
  • [37] Analysis and simulation of interconnects in high-speed integrated circuits
    Chowdhury, S.
    Daisun, Z.
    Bai, E.W.
    Lonngren, K.E.
    Proceedings - IEEE International Symposium on Circuits and Systems, 1991, 4 : 2379 - 2382
  • [38] SUB-20 PS HIGH-SPEED ECL BIPOLAR-TRANSISTOR WITH LOW PARASITIC ARCHITECTURE
    IINUMA, T
    ITOH, N
    NAKAJIMA, H
    INOU, K
    MATSUDA, S
    YOSHINO, C
    TSUBOI, Y
    KATSUMATA, Y
    IWAI, H
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (03) : 399 - 405
  • [39] ECL TECHNOLOGY SUITS HIGH-SPEED LOGIC SYSTEMS
    CHAN, K
    EDN, 1986, 31 (02) : 153 - &
  • [40] Novel Circuit Technique for High-speed ECL Gates
    Ishii, Kiyoshi
    Suzuki, Katsuya
    Sugimoto, Yoshihiro
    2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 89 - 92
12345