Linearity optimization of current steering DAC based on improved layout topology

被引：1
|
作者：
Tong, Xingyuan [1 ]
Wang, Chaofeng [1 ]
Wang, Fengjuan [2 ]
机构：
[1] Xian Univ Posts & Telecommun, Sch Elect Engn, Xian, Shaanxi, Peoples R China
[2] Xian Univ Technol, Sch Automat & Informat Engn, Xian, Shaanxi, Peoples R China
来源：
2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2019年
基金：
中国国家自然科学基金;
关键词：
Digital-to-Analog Converter; Segmented current steering; Random layout; Nonlinearity; COMPENSATION;
D O I：
10.1109/edssc.2019.8754219
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The influence of current mismatch on linearity of current steering DAC is theoretically discussed. Q(2) random walk scheme that can reduce the secondary error of current mismatch is utilized for optimizing the linearity of DAC. A 10 bit DAC is realized in 0.18 pm CMOS. Measurement results show that the differential non-linearity (DNL) and the integral non-linearity (INL) of the DAC are 0.71 LSB and 1.02 LSB. With 500 MS/s sampling rate and 1.465 MHz input frequency, the spurious free dynamic range (SFDR) and the effective number of hits (ENOB) are 65.6 dB and 9.2 bit, respectively.
引用
收藏
页数：3
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