Lagrangian Relaxation Based Topology Synthesis for Application-Specific Network-on-Chips

Application-Specific Network-on-Chip (ASNoC) has been proposed as a promising solution for addressing the global communication challenges in nanoscale System-on-Chips. However, with the number of cores on chip increasing, the power consumption and communication latency impose the major challenges for designing ASNoCs. In this paper, we propose an efficient latency-aware ASNoC low power synthesis algorithm. Firstly, considering the communication requirements and latency constraints between the cores, we integrate the floorplanning and clustering to explore the optimal clustering of cores. After the switches and network interfaces are inserted into the floorplan, a path allocation method based on the lagrangian relaxation is proposed for routing traffic flows with minimization of power consumption subject to the latency constraints. Experimental results show that the proposed method is highly efficient and the success rate for meeting the latency constraints of the traffic flows is up to 100%.