Automating the CMOS Gate Sizing For Reduced Power/Energy

被引：2

作者：

Beg, Azam ^{[1
]}

机构：

[1] United Arab Emirates Univ, Coll Informat Technol, Al Ain, U Arab Emirates

来源：

PROCEEDINGS OF 2014 12TH INTERNATIONAL CONFERENCE ON FRONTIERS OF INFORMATION TECHNOLOGY | 2014年

关键词：

low-power circuit; low-energy circuit; CMOS; logic gates; transistor sizing; static noise margin; proportional-integral-derivative (PID) feedback control; DESIGN; VOLTAGE; MODEL;

D O I：

10.1109/FIT.2014.44

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal, uniformly sized counterparts. Power and energy savings for NOR2-4 gates are up to 8% and 38%, respectively.

引用

页码：193 / 196

页数：4

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