EXPERIMENTS WITH POWER OPTIMIZATION IN GATE SIZING

被引：0

作者：

CHEN, GQ

ONODERA, H

TAMARU, K

机构：

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 1994年 / E77A卷 / 11期

关键词：

LOW POWER DESIGN; POWER DISSIPATION; GATE SIZING; AREA-POWER-DELAY TRADEOFF;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delay and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area-power-delay tradeoff in the gate sizing procedure.

引用

页码：1913 / 1916

页数：4

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