Positive Bias Temperature Instabilities in Vertical Gate-all-around poly-Si Nanowire Field-effect Transistors

Aiming at providing insight into the reliabilities of three-dimensional NAND flash memories with poly-Si channel, this work experimentally studied the positive bias temperature instability (PBTI) in vertical gate-all-around (GAA) poly-Si nanowire field-effect transistors (FETs). On the one side, the carrier-transport properties in the poly-Si nanowire are studied in a wide temperature range. On the other side, threshold voltage shifts, subthreshold slope, and transconductance under positive bias stress are measured, showing that the interface degradation takes place in a time scale much shorter than that of the V-th shift. These findings can be rationalized by the presence of serious trap charging in the gate dielectrics.