Sequential equivalence checking using cuts

被引：0
|
作者：
Huang, Wei [1 ]
Tang, PuShan [1 ]
Ding, Min [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
来源：
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an algorithm which is an improvement of Van Eijk's Algorithm[5] by incorporating a cutpoints technique[8]. Combinational verification often uses the technique to convert large scale circuits to several small ones, which will be verified separately. Reasonable cuts can bring less time consuming to combinational verification. We embed the technique into sequential equivalence checking. Experimental results show that the proposed method can achieve about 2x speedup over the original one.
引用
收藏
页码：455 / 458
页数：4
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