A New Hardware Implementation Of The H.264 8x8 Transform And Quantization

被引：7

作者：

Park, Jeoong Sung ^{[1
]}

Ogunfunmi, Tokunbo ^{[2
]}

机构：

[1] Santa Clara Univ, Dept Comp Engn, Santa Clara, CA 95053 USA

[2] Santa Clara Univ, Dept Elect Engn, Santa Clara, CA 95053 USA

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1- 8, PROCEEDINGS | 2009年

关键词：

H.264; integer transform; quantization;

D O I：

10.1109/ICASSP.2009.4959651

中图分类号：

O42 [声学];

学科分类号：

070206 ; 082403 ;

摘要：

H.264/AVC is the most powerful technology in video compression/transmission area because of its high coding efficiency and robustness. In this paper, we propose a new hardware architecture of W integer transform and quantization for H.264 which promises very low resource utilization. In the architecture, each pixel is processed one by one on a simplified pipeline without multiplication. Thus, redundant modules, which are used for block-based or row-based parallel processing, can be reduced. Experimental results show that it can reduce resource usage 30% compared to previously proposed models. It can be used for mobile applications. It covers a wide range of parameters as well.

引用

页码：585 / +

页数：2

共 50 条

[41] Implementations of low-cost hardware sharing architectures for fast 8 x 8 and 4 x 4 integer transforms in H.264/AVC
Fan, Chih-Peng
Lin, Yu-Lian
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2007, E90A (02) : 511 - 516
[42] An implementation of intra prediction with transform for H.264/AVC
Lee, Eunchong
Yoo, Jeongwoo
Ye, Sangwoo
Hong, Youpyo
IEICE ELECTRONICS EXPRESS, 2013, 10 (15):
[43] VLSI architecture & implementation of H.264 integer transform
Raja, G
Khan, S
Mirza, MJ
17th ICM 2005: 2005 International Conference on Microelectronics, Proceedings, 2005, : 218 - 223
[44] A proposed hardware reference model for spatial transformation and quantization in H.264
Amer, Ihab
Badawy, Wael
Jullien, Graham
JOURNAL OF VISUAL COMMUNICATION AND IMAGE REPRESENTATION, 2006, 17 (02) : 533 - 552
[45] Fast 2-dimensional 8 x 8 integer transform algorithm design for H.264/AVC fidelity range extensions
Fan, Chih-Peng
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, E89D (12) : 3006 - 3011
[46] Quantum circuit design of 8x8 discrete Hartley transform
Tseng, CC
Hwang, TM
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS, 2004, : 397 - 400
[47] Efficient hardware implementation for H.264/AVC motion estimation
Bojnordi, Mahdi Nazm
Semsarzadeh, Mehdi
Hashemi, Mahmoud Reza
Fatemi, Omid
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1749 - +
[48] An Efficient Hardware Implementation for H.264 Binary Arithmetic Encoder
Zargari, Farzad
Azimi, Ehsan
2009 14TH INTERNATIONAL COMPUTER CONFERENCE, 2009, : 105 - 109
[49] An Efficient Hardware Implementation of H.264 TQ/IQT Module
Loukil, H.
Ben Atitallah, A.
Kadionik, P.
Masmoudi, N.
2010 9TH INTERNATIONAL SYMPOSIUM ON ELECTRONICS AND TELECOMMUNICATIONS (ISETC), 2010, : 337 - 340
[50] A Hardware Efficient Implementation of Chroma Interpolator for H.264 Encoders
Wang, Teng
Zhao, Lei
Hu, Ziyi
Xie, Zheng
Wang, Xin'an
2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2011,

← 1 2 3 4 5 →