Design of Reversible Floating Point Adder for DSP Applications

Motivation for the study of technologies implementing reversible computing methods are that they offer a potential way to improve the energy efficiency of computers beyond the fundamental von Neumann-Landauer limit. Several implementations of floating-point unit in reversible logic have been suggested; and it has been found that the floating point addition is the most frequently used operation. In this paper, we present a reversible 16-bit floating-point adder that closely follows the IEEE-754 specification for binary floating-point arithmetic. The implementation of the floating-point adder using carry-lookahead adder and Brent-Kung adder structures have been designed and its performance parameters such as quantum cost, depth, garbage outputs, ancilla inputs, and delay have been compared. The proposed design has been extended to 32-bit to compare with existing works.