A Low Power Approach to Floating Point Adder Design for DSP Applications

The demand for high performance, low power floating point adder cores has been on the rise during the recent years particularly for DSP applications. In this paper, we present a new architecture for a low power, IEEE compatible, floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, clock gated data paths allows activity reduction. The switching activity function of the proposed adder is represented as a three state FSM. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipatory logic as well as data path simplifications. In contrast to conventional high speed floating point adders that use leading zero anticipatory logic, the proposed scheme offers a worst case power reduction of 50%.