A New Design Paradigm for Floating Point DSP Applications Based on ESL/HLS and FPGAs

Digital signal processing has emerged in every aspect of modern life, with different implementations found in appliances ranging from simple answering machines to high speed multimedia cloud routers. The design of such appliances requires a number of decision steps, based on diverse criteria like time-to-market, development cost, production cost, production volume, performance, power consumption and algorithm complexity, to name just a few. A crucial decision step is the use of a floating or fixed-point number representation. This paper presents a new paradigm for the design of floating point applications, based on modern hardware design techniques like electronic system level design and high-level synthesis, and the computing capabilities and power efficiency of modern FPGA devices. Specifically, it presents the design of a reusable, floating point, hardware operator library, starting from an open source software implementation. The advantages of this new paradigm is productivity improvement and ease of integration, through the use (or reuse) of C level input specifications, and performance improvements, by applying a set of specific C level hardware coding guidelines. As found through extensive experimentation, performance and area optimizations offered by these guidelines can be even more than 90%. Such results make the presented methodology an appealing and very promising design alternative.