A parametric design of a built-in self-test FIFO embedded memory

被引：7

作者：

Barbagallo, S

Bodoni, ML

Medina, D

DeBlasio, G

Ferloni, M

Fummi, F

Sciuto, D

机构：

来源：

1996 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 1996年

关键词：

D O I：

10.1109/DFTVS.1996.572028

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type FIFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a rest procedure the appropriate Built-In Self rest architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented.

引用

页码：221 / 229

页数：9

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