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- [1] Reconfigurable Hardware Architecture of the Spatial Pooler for Hierarchical Temporal Memory 2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), 2015, : 143 - 148
- [2] A robust implementation of the Spatial Pooler within the theory of Hierarchical Temporal Memory (HTM) 2013 6TH ROBOTICS AND MECHATRONICS CONFERENCE (ROBMECH), 2013, : 70 - 73
- [4] Using Spatial Pooler of Hierarchical Temporal Memory for object classification in noisy video streams PROCEEDINGS OF THE 2016 FEDERATED CONFERENCE ON COMPUTER SCIENCE AND INFORMATION SYSTEMS (FEDCSIS), 2016, 8 : 271 - 274
- [5] Hierarchical Temporal Memory implementation on FPGA using LFSR based spatial pooler address space generator 2017 20TH IEEE INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUIT & SYSTEMS (DDECS), 2017, : 92 - 95
- [7] Feature extraction without learning in an analog spatial pooler memristive-CMOS circuit design of hierarchical temporal memory Analog Integrated Circuits and Signal Processing, 2018, 95 : 457 - 465
- [10] Hierarchical Temporal and Spatial Memory for Gait Pattern Recognition 2016 IEEE APPLIED IMAGERY PATTERN RECOGNITION WORKSHOP (AIPR), 2016,